In recent years, with an increase in speed of a digital signal processing, a high processing speed is also demanded in an output buffer circuit. As a conventional output buffer circuit, an output buffer circuit having a complementary metal oxide semiconductor (CMOS) configuration using a transistor having a high current drive capability for increasing processing speed is known. FIG. 14 is a circuit diagram showing a rough configuration of a conventional output buffer circuit. The conventional output buffer circuit comprises an inverter circuit 91 serving as a pre-driver and a final CMOS output circuit in which a p-channel MOS transistor QP0 having a high drive capability and an n-channel MOS transistor QN0 are connected in series with each other. A load capacitor CL is connected to the output terminal of the final CMOS output circuit extracted from the node between the p-channel MOS transistor QP0 and the n-channel MOS transistor QN0.
Operation of the conventional output buffer circuit will be described below. FIG. 15 is a timing chart showing the operation of the conventional output buffer circuit. In the operation of the conventional output buffer circuit, when an input signal Vin input to the inverter circuit 91 is at an "L" level, an output signal A0 from the inverter circuit 91 goes to an "H" level, the p-channel MOS transistor QP0 is turned OFF, and the n-channel MOS transistor QN0 is turned ON. In this manner, the load capacitor CL is in a discharge state, and an output signal Vout0 from the output buffer goes to an "L" level.
When the level of the input signal Vin changes from an "L" level to an "H" level, the level of the output signal A0 from the inverter circuit 91 changes from an "H" level to an "L" level, the p-channel MOS transistor QP0 is turned ON, and the n-channel MOS transistor QN0 is turned OFF. In this manner, the load capacitor CL is charged, and the output signal Vout0 goes to an "H" level. In addition, the level of the input signal Vin changes from an "H" level to an "L" level again, the level of the output signal A0 from the inverter circuit 91 changes from an "L" level to an "H" level, the p-channel MOS transistor QP0 is turned OFF, and the n-channel MOS transistor QN0 is turned ON. In this manner, electric charges charged in the load capacitor CL are discharged, and the output signal Vout0 goes to an "L" level.
In order to increase the processing speed of the output buffer circuit, the current drive capabilities of the p-channel MOS transistor QP0 and the n-channel MOS transistor QN0 serving as output transistors are made high. In this case, when the load capacitor CL is large, the inductances of the load capacitor CL and a wire or the like resonate. When the output signal Vout0 rises or drops, overshoot, undershoot, and ringing occur. The principle behind the occurrence of ringing and the like occur will be described below with reference to FIG. 16. FIG. 16 is a circuit diagram showing a rough equivalent circuit of the conventional output buffer circuit in a state wherein a signal having an "L" level is output, i.e., the n-channel MOS transistor QN0 is turned ON.
In the equivalent circuit of the conventional output buffer circuit, the n-channel MOS transistor QN0 is represented by a circuit in which a current source 92 and an ON resistor Ron are connected in parallel to each other. A load connected to an output terminal 93 of the output buffer circuit is expressed by a circuit obtained such that an inductance 94 constituted by a wire, a pattern on a printed board, a bonding wire of an integrated circuit, or the like is connected in series with a load capacitor 95. In this manner, an equivalent circuit including the output buffer circuit and the load constitutes an LCR resonance circuit. A resonance frequency f0 of the LCR resonance circuit and a value .theta. obtained at the resonance frequency are expressed by the following equations: EQU f0=1/(2.pi..multidot.SQRT(LC))
.theta.=j.omega.0.multidot.L/Ron
where 2.pi.f0=.omega.0, and SQRT(X) represents the square root of X.
In this case, as the current drive capability of the output transistor is increased to increase the processing speed of the output buffer circuit, the ON resistor Ron of the output transistor decreases. Accordingly, the value .theta. increases and the output buffer circuit resonates due to a change in level of the input signal Vin0 from an "H" level to an "L" level, so that ringing or the like of the output signal Vout0 occurs.
However, according to the prior art described above, when the current drive capability of the output transistor is excessively increased to increase the processing speed of the output buffer circuit, overshoot, undershoot, and ringing occur when the output signal Vout0 rises or drops. The overshoot, undershoot, and ringing may generate noise in signal transmission, and may cause an erroneous operation of a logic circuit system. In addition, the overshoot, undershoot, and ringing may be a factor called an undesired reflection which generates jamming waves to another electronic equipment. Thus, an increase in current drive capability of the output transistor is limited to a specific level, and a desired high-speed operation cannot be performed.